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AM79C961AKCW datasheet

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Category: Electronics
Forum Name: IC datasheets
Forum Description: Datasheet for ICs
URL: http://www.serasidis.gr/forum/forum_posts.asp?TID=294
Printed Date: 19 May 2013 at 04:13
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Topic: AM79C961AKCW datasheet
Posted By: Cristinalee
Subject: AM79C961AKCW datasheet
Date Posted: 24 May 2008 at 03:53

http://www.chinaicmart.com/suppliers/131/AM79C961AKCW.html - AM79C961AKCW pdf and datasheet download :

GENERAL DESCRIPTION
The PCnet-ISA II controller, a single-chip Ethernet con-FIFOs, IEEE 802.3 defined Attachment Unit Interface troller, is a highly integrated system solution for the(AUI), and a Twisted Pair Transceiver Media Attach-PC-AT Industry Standard Architecture (ISA) architec-ment Unit. Full duplex network operation can be ture. It is designed to provide flexibility and compatibil-enabled on any of the device¡¯s network ports. The ity with any existing PC application. This highlyPCnet-ISA II controller is also register compatible with integrated 132-pin VLSI device is specifically designedthe LANCE (Am7990) Ethernet controller and to reduce parts count and cost, and addresses applica-PCnet-ISA. The DMA Buffer Management Unit sup-tions where higher system throughput is desired. Theports the LANCE descriptor software model. External PCnet-ISA II controller is fabricated with AMD¡¯sremote boot and Ethernet physical address PROMs advanced low-power CMOS process to provide lowand Electrically Erasable Proms are also supported. standby current for power sensitive applications. This advanced Ethernet controller has the built-in The PCnet-ISA II controller can be configured into onecapability of automatically selecting either the AUI port of three different architecture modes to suit a particularor the Twisted Pair transceiver. Only one interface is PC application. In the Bus Master mode, all transfersactive at any one time. The individual 136-byte transmit are performed using the integrated DMA controller.and 128-byte receive FIFOs optimize system over- This configuration enhances system performance byhead, providing sufficient latency during packet trans- allowing the PCnet-ISA II controller to bypass the plat-mission and reception, and minimizing intervention form DMA controller and directly address the full 24-bitduring normal network error recovery. The integrated
memory space. The implementation of Bus MasterManchester encoder/decoder eliminates the need for mode allows minimum parts count for the majority ofan external Serial Interface Adapter (SIA) in the node PC applications. The PCnet-ISA II can also be config-system. If support for an external encoding/decoding
ured as a Bus Slave with either a Shared Memory orscheme is desired, the embedded General Purpose Programmed I/O architecture for compatibility withSerial Interface (GPSI) allows direct access to/from the low-end machines, such as PC/XTs that do not supportMAC. In addition, the device provides programmable
Bus Masters, and high-end machines that require localon-chip LED drivers for transmit, receive, collision, packet buffering for increased system latency.receive polarity, link integrity and activity, or jabber status. The PCnet-ISA II controller also provides an The PCnet-ISA II controller is designed to directly inter-
TMTM External Address Detection Interface (EADI) to face with the ISA or EISA system bus. It contains an allow external hardware address filtering in internet-
ISA Plug and Play bus interface unit, DMA Buffer Man- working applications.




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